Software tool to allow field programmable system level devices

ABSTRACT

A method and system for co-verifying a hardware simulation of a field-programmable-system-level integrated circuit (FPSLIC) and a software simulation of the field-programmable-system-level integrated circuit. A FPSLIC device is simulated in hardware, and a simulator-port layout of the FPSLIC device is generated. In software, the method separately simulates, with an instruction-set simulator, the FPSLIC device, and outputs register contents from the instruction-set software. The contents from the simulator-port layout are verified with the register contents. Additionally, the method may further include outputting peripheral contents from the instruction-set simulator, and verifying contents from the simulator-port layout with the peripheral contents. UART contents also may be outputted from the instruction-set simulator, and verified with contents from the simulator-port layout with the UART contents.

BACKGROUND OF THE INVENTION

[0001] This invention relates filed programmable system level integratedcircuits (FPSLIC), and more particularly to a method and system forco-verifying a hardware simulation and a software simulation of a FPSLICdevice.

DESCRIPTION OF THE RELEVANT ART

[0002] System level integration (SLI) is rapidly becoming the preferredway to implement electronic designs. Integrating all the systemfunctionality in a system-level integrated circuit (IC) increasesperformance, reduces power consumption, cuts unit production costs andallows smaller products. These are particularly important benefits intelecommunications, multimedia and networking applications.

[0003] A “system” consists of three main building blocks: a processor,memory and logic. Usually, the processor is used for control flow logic,the memory is used for program and data storage and the logic is usedfor datapath logic. A true system-level solution must contain all threeelements.

The ASIC Solution

[0004] Until now, system level integration has been implemented incell-based or masked application specific integrated circuits (ASICs),because these were the only solution available with sufficient densityto handle system level designs. Unfortunately, ASICs have highnon-recurring engineering (NRE) costs, long lead times and significantminimum order quantities. As a result, system level ASIC implementationshave been accessible only to the highest volume designs with relativelylong product life cycles. Minimum volume requirements for system-levelASIC devices currently are often more than $500K per design per year.Designs with short product life cycles, low to medium volumes, time tomarket pressures or rapidly evolving standards can not afford thelengthy development cycle, risk and high NRE charges associated with anASIC solution.

[0005] Even when the volume/dollar criteria are met for an ASICsolution, any change in the design to correct an error or improve itleaves the developer with a large inventory of possibly useless partsand another lengthy ASIC design cycle. This is particularly problematicfor rapidly evolving designs such as those in telecommunications,networking and multimedia. For these and other designs a programmablesolution is preferable because the design can be changed at will bothduring development and in the field. ASIC solutions are not an optionfor these designs.

[0006] A substantial number of these rapidly evolving designs areimplemented in a combination of programmable logic, discrete standardproducts (microcontrollers, memories) and Application Specific StandardProducts (ASSPs), such as T1 Interface, ATM, 10/100 PHY, and Video/AudioCodecs. Although this approach offers the flexibility to evolve designsrapidly it does not offer the performance, power, space and reliabilityadvantages of a monolithic system level integrated circuit. Asingle-chip, programmable solution is clearly the preferablealternative.

Multiple Approaches to Programmable System Level Integration

[0007] Field programmable gate array (FPGA) and other IC vendors havedeveloped a variety of approaches to providing programmable system levelintegration. These include “pure play” high-density FPGAs and hybriddevices that combine both FPGA and fixed logic functionality.

[0008] The mostly widely promoted means of achieving programmable SLItoday are Xilinx's Virtex® and Altera's APEX® FPGA families that boastas many as a million gates. Although industry analysts believe thesegate counts may be substantially overstated, these devices are stilllarge enough to support system level integration of designs that mightotherwise go into a masked- or cell-based ASIC. FPGAs now compete withmasked-ASICs in terms of both density, and in the case of low densityFPGAs, price. High density FPGAs are being proposed as a programmable,single-chip solution for system level integration. Although theprogrammability of the large FPCAs is very attractive, they have somesignificant drawbacks:

[0009] Although deep sub-micron process technologies have reduced theprices of low and medium density FPGA so that in many cases FPGA pricesare on a par with those of ASICs, high gate count devices are extremelyexpensive. For example, Xilinx's million gate Vertex XCV1000 devicecurrently sells for $4,298.00 each. The extremely high prices of thesedevices limits their use to ASIC prototyping and production runs of ahandful of very high priced products. When one considers that amasked-ASIC of comparable density cost about $50, these large FPGAs areout of reach for most volume designs/applications.

[0010] Although FPGA devices can cut the ASIC development cycle in half,the complexity of large FPGAs mandates a significant design anddevelopment process for system level designs. Today ‘time-to-market’ isthe difference between success and failure of a product. Designing amillion gates of FPGA logic takes a great deal of time. Frequentlyintellectual property (IP) cores are used to reduce the design cycle.However, integrating vendor supplied soft IP into a design is in itselfoften a cumbersome and time-consuming process.

[0011] Simulation is another problem with large FPGAs. HDL simulationsare notoriously slow for simulating large designs, especially ones usingcomplex soft IP cores. Simulating a one million gate FPGA design cantake so long that many designers simulate less thoroughly than isdesirable or not at all. The result is that these designs are morelikely to have undiscovered bugs that extend the debug cycle, furtherdelaying product introductions.

[0012] This problem is further amplified if a microcontroller soft IPcore is being used in a large FPGA design. Conventional MCU designmethodologies are not available to the designer in the large FPGA baseddesign flow. Typically, microcontroller designers have code developmentand debugging tools that are used to debug the microcode. These toolsare often not available for soft IP cores used on a large FPGA, so codedevelopment and debugging are problematic if not impossible.Furthermore, because of the lack of code development and debugging toolsavailable for processor cores, the integration and debug of themicrocontroller portion of a these designs is extremely difficult.Similar arguments can easily be made for timing analysis on system-levelFPGA designs.

[0013] One solution to the complexity of designing system-level FPGAs isto use “drop-in” soft intellectual property cores. Memory, logic and alimited number of processor IP cores can be purchased from third partyvendors and dropped into large FPGAs. However, soft IP cores areexpensive, difficult to integrate in the design, and tend to be siliconinefficient. The difficulty of integrating IP cores from differentthird-party vendors can significantly extend the product developmentcycle. For example, an 8051 core for the Xilinx Virtex, supplied byDolphin in France, costs over $10,000 to license and uses 1010 CLBs or16.4% of a XCV1000. At a list price of $4,298 for each XCV1000, thesilicon cost of the 8051 core is $704, excluding the cost of the coreitself.

[0014] “The Flip-8051 core forms the heart of a family of processorsthat include lower performance options as well as microcontrollerconfigurations that include peripherals such as timers and serialinterfaces. Pricing starts as low as $10,000 for an EDIF format forVirtex FPGAs. Other design file formats are available. A VHDLsource-code version is available with a test bench at extra cost. Mar.23, 1999-Xilinx Inc.

[0015] There are additional design problems associated with building theinterfaces between the various cores and correcting timing problems.Studies have shown that up to one half of the typical design project isspent in the integration and test phase, which in reality becomes anexercise in correcting the accumulation of errors from the front end ofthe design cycle. These problems are magnified when multi-site,multi-engineer development teams work on large FPGA-based systems. Theerrors often reach all the way back to the specification andpartitioning phase, where ambiguities in the hardware/software interfacewere introduced and then amplified during the hardware/softwareimplementation phase. Often, the remedy of these errors is forced intosoftware due to the long lead times and high cots of ASIC or large FPGAturns—even though a software fix may result in compromised performanceor functionality in the final product.

[0016] Although FPGAs represent an efficient means of implementingdata-path functions, control logic is better suited to a CPLD ormicrocontroller architecture. FPGA implementations of control logic arenot silicon efficient. This is demonstrated by the architectural changesthat Altera has implemented in their next generation large FPGAs. Theinclusion of CPLD blocks of logic in these large devices clearly shows aweakness in implementing control flow logic in current homogeneous largeFPGA solutions. The inclusion of CPLD structures helps control flow inthe Altera APEX architecture, however, the CPLD solution is still lessefficient than a microcontroller at implementing control flow anddecision making.

[0017] For example, a mail sorting system must acquire the visual dataon each piece of mail using a high speed camera, convert the data fromanalog to digital, pre-process it to identify the location andorientation of the address, process the address pixels to decode theaddress and then generate machine readable code that can be read by thesorting machine. Just identifying the address in the image requires anenormous amount of data processing because each pixel has to be comparedto all the pixels surrounding it. Since so much of the image is likelyto be irrelevant, it would be inefficient and slow to process the entireimage with a processor. FPGA based DSP algorithms can be used to filterout those portions of the image that are not likely to be part of thestreet address. This process eliminates most of the image, therebycutting the processing problem to a manageable size. FPGAs are ideal forthese types of operations and can perform them significantly faster thana DSP processor.

[0018] A processor, on the other hand, performs the algorithms for imageextraction, de-skewing, rotation and data interpretation much moreefficiently than an FPGA. FPGAs are inadequate to these tasks becausethe amount of complex ‘decision’ making involved (control flow). Theyare simply too slow at performing control flow tasks. Implementing aprocessor that is capable of the tasks outlined above using FPGA corecells (LABs/CLBs) is difficult and very silicon inefficient andtherefore very expensive. Since all systems contain both datapath andcontrol flow logic, system level integration in a general purpose FPGAcannot ever be terribly efficient. In short, on its own, a generalpurpose FPGA is not a solution.

[0019] Power consumption has three components: static power consumption,dynamic power consumption, and input/output (I/O) or system powerconsumption. Static power consumption is a function of the number oftransistors in the device and increases with the size of the FPGA.However, with careful design even large FPGAs can have very low staticpower consumption. The second source of power consumption, dynamic powerconsumption, is consumed in the I/O structure. Significant power isdissipated each time an output switches from one logic state to another.Capacitive loading on the printed circuit board (PCB) is the reason forthis power consumption. Reducing the number of parts in a system throughintegration significantly reduces this aspect of system powerconsumption. Since most large FPGAs still have to connect to thehigh-bandwidth microcontroller bus, significant power is consumedthrough this interface.

[0020] The third component of power consumption is dynamic. Thecombination of a large numbers of core cells for design implementationand the internal clock distribution tree significantly contribute topower consumption. Thus the larger FPGAs that must be used for SLIdesigns draw proportionately more power. Programmable SLI in a largeFPGA is likely to consume a great deal of power.

[0021] Because of the above issues, just increasing the density of FPGAsis probably not the most practical solution to achieving programmabilitywith system level integration.

[0022] Recently, a handful of fabless IC start-ups have developed hybriddevices that integrate blocks of programmable logic with a hard-wiredmicroprocessor cores. The introduction of these devices indicates theneed for products that address the SLI needs of the systems architect.

[0023] These devices are too specialized to fall into the generalpurpose SLI category. For example, Triscend's configurable 8052 EV5microcontroller is positioned as a replacement for a single-chip MCUwith peripherals that are programmed into an on-chip FPGA with 5,000 to30,000 gates. These devices provide embedded systems designers customMCU derivatives without having to order the 100,000 units conventionalMCU vendor require to consider creating a derivative.

[0024] Another silicon valley start-up is Chameleon Systems which hasannounced a yet to be introduced “reconfigurable network processor”.Although product details have not yet been disclosed, all indicationspoint to a specialized product that addresses specifictelecom/networking applications.

[0025] Chameleon will focus on the complex communication processingrequirements between the physical interface (PHY) and the switch fabricprevalent in the convergence of the data networking and telecom markets.

[0026] Specialized FPGA Based Devices: Both Lucent Technologies andQuicklogic have announced FPGAs that include specialized functions, suchas PCI. However neither company has introduced a true system-levelproduct, with a processor, memory and datapath logic.

[0027] None of these solutions provides truly programmable system levelintegration, namely programmable logic, microcontroller and memory, withdesign tools that support system-level design methodology.

SUMMARY OF THE INVENTION

[0028] A general object of the invention is to allow programmable logicusers to design, with ease, FPSLIC devices that contain complex blocks,such as, but not limited to, microprocessors such as AVR, ARM and 8051,embedded memory blocks such as RAMs, ROMs and EEPROMs, interfacecircuitry such as SPI, USB, PCI and I²C, and FPSLIC devices such asAT40K.

[0029] Another object of the invention is a software tool which acts asa design and methodology flow manager.

[0030] An additional object of the invention is a software tool whichhas design flow through the various CAE development tools changes basedon the device selected in the design manager.

[0031] According to the present invention, as embodied and broadlydescribed herein, a method for co-verifying a hardware simulation of afield-programmable-gate array (FPGA) and a software simulation of thefield-programmable-gate array, is provided. The method comprises thesteps of simulating, in hardware, a FPGA device, and generating, fromthe simulation in hardware, a simulator-port layout of the FPGA device.

[0032] A FPSLIC device includes field programmable gate array (FPGA)core, a microcontroller, and memory. The FPGA core includes a pluralityof gates, which may be, for example, an SRAM-based FGPA eight-sidedlogic cell architecture. The logic cell architecture performs complexfunctions without impacting bus resources.

[0033] The plurality of gates are programmable by an external NVM,configuration memory, or the microcontroller. For example, a specificapplication requires a program in the microcontroller to set the FPSLICdevice FPGA programmable logic for the application. In manyapplications, the logic in the FPGA is loaded at power-up.

[0034] Software for the application may be stored in the memory. Thememory includes dynamic-allocation-program memory, fixed-data memory,and a memory controller. The dynamic-allocation-program memory might be,by way of example, a 32 kilobyte (16K×16 or 32K×8) block of 20nanoseconds SRAM for program instruction storage. If not all 32kilobytes were required, then the program memory may be partitionedduring design development into eight 4 kilobyte blocks to provideadditional data memory storage. Additionally, fixed-data memory may beeight four kilobyte, or increased by adding partitions fromdynamically-allocation-program memory.

[0035] A hardware-multiplication accelerator enables the microcontrollerto perform complex digital signal processor (DSP) operations quickly andefficiently.

[0036] Additional objects and advantages of the invention are set forthin part in the description which follows, and in part are obvious fromthe description, or may be learned by practice of the invention. Theobjects and advantages of the invention also may be realized andattained by means of the instrumentalities and combinations particularlypointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings, which are incorporated in andconstitute a part of the specification, illustrate preferred embodimentsof the invention, and together with the description serve to explain theprinciples of the invention.

[0038]FIG. 1 is a block diagram of an FPSLIC device;

[0039]FIG. 2 illustrates co-verification of hardware and software, flowand simulation; and

[0040]FIG. 3 is a flowchart of a hardware flow and simulation and asoftware flow and simulation, with co-verification.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0041] Reference now is made in detail to the present preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings, wherein like reference numerals indicate likeelements throughout the several views.

[0042] The ever-increasing time to market requirements of fieldprogrammable gate arrays makes necessary a software tool which managesand tightly integrates various discrete ‘point’ computer aidedengineering (CAE) tools. The CAE tools can be used extensively bydesigners to develop code for FPSLIC devices.

[0043] The present invention combines programmability with system levelintegration, to develop a family of system level integrated circuits(ICs) with specific dedicated functionality that provides a siliconefficient means of creating a system on a chip. The Field-ProgrammableSystem Level ICs (FPSLIC), by way of example, include an ATMEL AT40KFPGA for datapath logic, the RISC-based AVR microcontroller for controllogic, a hardware multiplier, MCU peripherals and 32 Kbytes of SRAM: allthe building blocks of a system. The FPSLIC architecture is ideal forthe implementation of networking, telecommunications, multimedia, audio,handheld, portable and industrial control applications.

[0044] As illustratively shown in FIG. 1, a field programmable systemlevel integrated circuit (FPSLIC device) 20 includes field programmablegate array (FPGA) core 21, a microcontroller 22, and memory. The FPGAcore includes a plurality of gates, shown as SRAM-based AT40K FGPAeight-sided logic cell architecture 75. The logic cell architecture 75performs complex functions without impacting bus resources. Discretefree-RAM ten nanoseconds dual port SRAM blocks 74 are located at thecorners of each 4×4 cell sector. Locating these SRAM blocks throughoutthe array puts memory where it is needed, and supports high-performancefirst-in-first-out (FIFO) designs.

[0045] The plurality of gates are programmable by an external NVM,configuration memory, or the microcontroller 22. For example, a specilicapplication requires a program in the microcontroller 22 to set theFPSLIC device FPGA programmable logic 21 for the application. In manyapplications, the logic in the FPGA is loaded at power-up. Software forthe application may be stored in the memory of the microcontroller 22.In operation, the microcontroller 22 sets to gates of the FPSLICprogrammable logic 21 for the application.

[0046] The memory includes dynamic-allocation-program memory 23,fixed-data memory 24, and a memory controller 25. Thedynamic-allocation-program memory 23 might be, by way of example, a 32kilobyte (16K×16 or 32K×8) block of 20 nanoseconds SRAM for programinstruction storage. If not all 32 kilobytes is required, then theprogram memory may be partitioned during design development into eight 4kilobyte blocks to provide additional data memory storage. Additionally,fixed-data memory 24 may be eight four kilobyte, or increased by addingpartitions 81 from dynamically-allocation-program memory 23.

[0047] A hardware-multiplication accelerator 29 enables themicrocontroller 22 to perform complex digital signal processor (DSP)operations quickly and efficiently.

[0048] The FPSLIC solution stems from a unique high performance FPGAarchitecture, and several microcontroller core technologies. The FPSLICemploys cell-based and masked ASIC and Application Specific StandardProduct (ASSP) development, the technology and expertise to combinethese functions into silicon efficient, cost effective system leveldevices.

[0049] The AVR based FPSLIC product incorporates Atmel's AT40K embeddedFPGA technology. The AT40K FPGA core is programmable logic which is afully PCI-compliant, SRAM-based FPGA with distributed ten nanosecondsprogrammable synchronous/asynchronous, dual port/single port SRAM, 68external global clocks and 2 AVR global clocks, Cache Logic ability(partially or fully reconfigurable without loss of data) and 10,000 to40,000 usable gates.

[0050] The microcontroller executes instructions in a single clockcycle, achieving throughput that approaches one MIPS per MHz. Thesubstantial throughput allows system architects to optimize powerconsumption versus processing speed. A 30 MIPS microcontroller core isbased on an enhanced RISC architecture that combines a rich instructionset with 32 general-purpose working registers. All the 32 registers aredirectly connected to the arithmetic logic unit (ALU), allowing twoindependent registers to be accessed in one single instruction executedin one clock cycle. The resulting architecture is more code efficientwhile achieving throughout up to ten times faster than conventional CISCmicrocontrollers.

[0051] The memory executes out of SRAM. Both the FPGA configurationmemory and microcontroller 22 instruction code SRAM can be automaticallyloaded at system power-up using Atmel's in system programmable AT17series EEPROM configuration memories. By combining the three main systembuilding blocks on a single programmable device, an high performancesystem level product is created which is flexible enough and costeffective enough to be used as a general purpose SLI device.

[0052] FPSLIC EDA tool suite, System Designer, provides a trulyintegrated system design methodology and suite of design tools. FPSLICis the only programmable solution to include co-verification tools asstandard. Co-verification facilitates the creation of virtualprototypes, which allows the problems typically encountered duringsystem integration to be resolved much earlier in the design cycle,resulting in a shorter design cycle. Co-verification also allows rapid‘what if’ trade-offs to be performed, fostering better systemefficiencies.

[0053] Both the FPSLIC silicon and the System Designer software havebeen engineered as a complete SLI solution to accelerate time to market.

Designing With FPSLIC

[0054] By integrating all the functionality required to create a systemlevel product in one programmable solution, FPSLIC devices present theuser with a comprehensive and integrated solution. The FPSLIC deviceclosely mimics a typical system level architecture. It has the commoninterfaces between microcontroller memory and logic already implementedallowing the designer to focus on the value added parts of the systemdesign without compromising flexibility or performance.

[0055] Use of existing standard design tools with the addition ofhardware/software co-verification means that reliable bug freemicrocontroller and FPGA development software is combined with softwarebased system level simulation. The result is an easy to use productivityenhancing development tool (System Designer) that allow concurrentsoftware and hardware design and dramatically accelerates designdevelopment and reduces a products time to market.

[0056] An AT94k0 FPSLIC devices implementation of the mail sortingexample described earlier would distribute system tasks in the followway: AT40K FPGA array in the FPSLIC device would pre-process thepixelized data to locate probable address candidates. The FPSLIC'smicrocontroller 22 and hardware multiplier would take over the imageextraction, rotation and de-skewing tasks. Intermediate data would bestored in the on-chip SRAM, allowing maximum system throughput to bemaintained.

[0057] This combination of memory (SRAM), logic (FPGA) and amicrocontroller 22 on a single SLI device provide for efficientimplementation of the data-path (logic) and control flow (AVRmicrocontroller) aspects of SLI design. Instead of ‘shoe-horning’ adesign into a homogeneous FPGA solution the FPSLIC devices provideefficient implementation of all aspects of the system. Siliconefficiency results in smaller die size, fast development times, highperformance designs and lower power consumption. So dramatic is theeffect with FPSLIC devices that device costs are two orders of magnitudeless than competing large FPGA solutions. The usual trade-off associatedwith silicon efficiency is a lack of flexibility—however the use of ahigh performance RISC microcontroller with FPGA and a dynamicallyallocated SRAM memory provides both efficiency and flexibility.

[0058] In FPSLIC devices the intellectual property (IP) required forsystem level integration is an inherent part of the device. AdditionalIP blocks can be added to FPGA (logic) part of the design, e.g. from thelibrary of parameterizable macro generators. Unlike large FPGAs thesimulation, placement and timing challenges of integrating soft IPprocessors have mostly been removed from the FPSLIC parts. Thisaccelerates time to market and allows the designer to focus on the valueadded aspects of the SLI design. Logic based soft IP cores can be usedon the FPSLIC device if required in the logic part of the design.

[0059] Multiple features in FPSLIC devices cut power consumptiondramatically, compared to the FPGA or discrete solution, including moreefficient use of logic resources. By including a “hard” microcontrollercore for the implementation of control logic, FPSLIC save power draininglogic resources. A “soft” microcontroller core in a large FPGA requiressubstantially more logic gates than that consume substantially morepower.

[0060] Since FPSLIC devices integrate all the required system blocksFPSLIC eliminates the I/O ports and capacitive loading associated withinter-device PCB connections significantly saving system power.

[0061] FPSLIC devices include the FPGA clocking tree structure, which ispartitioned into small segments so the FPSLIC device only drives clockslines to registers, as required. The clock partitioning can save 50%+ ofthe dynamic power consumption in the FPGA part of the FPSLIC device on atypical design.

[0062] The microcomputer 22 in the FPSLIC can achieve 30+ MIPSthroughput, allowing to be used in ‘burst-mode’ processing. Burst modeprocessing allows the AVR to perform the processing in very shortperiods of time and then be put into power-down mode for the majority ofthe time, saving substantial power.

[0063] The combination of FPGA and microcontroller in FPSLIC devicesallows partial reconfiguration of the FPGA core. Thus, a single designto be reconfigured to serve several purposes, saving both silicon andpower.

[0064] This in-system reconfigurability is particularly useful fordesigns which must be able to implement multiple standards, such as“soft radio” being developed for third generation mobile communications.A single FPSLIC could contain multiple mobile phone (base-band)standards that allow it to operate in any location or environment. In alocation where wide-band code division multiple access (W-CDMA) is thestandard, the W-CDMA design would be loaded into the FPSLIC device. Whenthe phone user traveled to a location where GSM was the standard, Europefor example, the FPSLIC device could be reconfigured on the fly with theGSM design. This would be entirely transparent to the user, but it wouldallow a single FPSLIC device to be used for many different system levelmobile phone standards.

[0065] Atmel's System Designer EDA tool suite supports reconfigurablecomputing by supporting incremental design changes, extensive librarycontrols and bitstream utilities, additional recofigurable computingtools will be available later in 1999.

[0066] In the near future personal digital assistants (PDAs), mobilephones, pagers and global positioning by satellite will all be squeezedinto a single, hand-held PDA-type device. The high performance,reconfigurability and very low power consumption of FPSLIC devices makethem ideal for these portable applications.

[0067] PDAs typically operate in different, dedicated, sequential modes.For example, in one mode the PDA captures the pen input. In another itperforms infrared data transfer. In a third mode, it could support modemtransfers. By using an in-system programmable SLI device such as FPSLIC,many modes can be supported in a single system-level IC efficiently andwith minimum power consumption.

[0068] In pen capture mode, the FPSLIC's FPGA would scan the screen andprocess the raw data, while the microcontroller 22 would handledecisions making and data display. If the PDA user decided that he/sheneeded to beam data to/from another user, the infrared logic mode (IrDlink) design would be loaded into the FPGA, replacing the pen capturemode. The reconfigured PDA would beam the data, using the AVRmicrocontroller to handle data packaging and compression, and using theFPGA to handle CRC checking, the physical layer logic and handshaking.After the transfer is complete, the IrD link logic would not be neededand the FPSLIC device might reconfigured to transfer data receivedserially to a back up PC or printer by loading the FPGA with a highperformance UART. (The FPSLIC on-chip UART could be also used.) Inshort, a single piece of FPGA silicon in the FPSLIC device can bere-used many times in different applications in the system.Reconfiguring the FPSLIC FPGA results in a smaller, lower power and morecost effective solution.

Design Tools

[0069] Designing, simulating and debugging an ASIC or ASSP design is adaunting task, at best. Designing a very large FPGA is equally ascumbersome. Even when the designer can, with confidence, drop in asoft-IP core of a microcontroller, he/she is faced with some seriousdesign tool challenges. Issues of place and route times, designcomplexity, interactions between IP from different IP vendors and designperformance are just some of the immense challenges facing designers oflarge FPGAs.

[0070] Unlike large FPGA design tool suites which have not changed toaccommodate the additional challenges associated with implementing SLI,the FPSLIC design tools concurrently are developed with the FPSLICarchitecture to ensure a seamless development environment between theprogrammable logic and microcontroller areas of the tool.

[0071] Design tools for the FPSLIC family has been to evolve itsestablished, ‘field-tested’ design tools. The design methodology remainsessentially unchanged from the methodology used for a discrete_solutionwith a microcontroller, FPGA and memory. The standard FPGA design toolssupport FPSLIC FPGA cores. The tools designers have been using to designAT40K FPGAs, such as macro generators, timing driven design,,HDLPlanner(tm), static timing analysis, back annotation, push button APRall work the same way in the FPSLIC System Designer development tools asthey do in Atmel's IDS FPGA design tools. The FPSLIC AVR developmenttools work identically to Atmel's AVR Studio. By using establishedstate-of-the-art software, Atmel has created comprehensive, verifiedsoftware solution.

System Designer Co-Verification EDA Tool Suite

[0072] FPGAs are usually designed using hardware description languages(HDLs), such as Verilog or VHDL and then simulated using an HDLsimulator. Microcontroller designs are usually done in the C-language orassembly and debugged using a software debugger or ICE (In-circuitemulator). The challenge Atmel faced was integrating these two solutionsinto an environment that not only allowed for easy product developmentand accelerated the designers time to market, but also allow thedesigner to do extensive ‘what if’ analysis between the hardware andsoftware aspects of the design very early in the design process.

[0073] Atmel has solved the problem of software/hardware co-design bydeveloping the System Designer Co-verification EDA tool suite. The needfor hardware/software co-verification has grown out of the productivityand time-to-profit obstacles inherent in the conventional design cycle.Up to half of the typical design project is spent in the integration andtest phase. In reality this is an exercise in correcting theaccumulation of errors from the front end of the design cycle. Theseerrors often reach all the way back to the specification andpartitioning phase, where ambiguities in the hardware/software interfacewere introduced and then amplified during the hardware/softwareimplementation phase. Often, the remedy of these errors is forced intosoftware due to the long lead times and high cots of ASIC turns—eventhough a software fix may mean compromised performance or functionalityin the final product.

[0074] System Designer seamlessly integrates Atmel's FPGA design toolsand a third party hardware (verilog/VHDL) simulator with its AVRmicrocontroller instruction simulator and debugging tools. In addition,a co-verification framework fully synchronizes hardware and softwareexecution, and source-and assembly-level software debugging. The toolsuite provides full visibility of the AVR memory and registers, and fullhardware design visibility. System Designer allows designers to do thecomplete hardware and software design with complete confidence.Software/hardware trade-offs can be made and tested until an optimizedimplementation is arrived at. Design cycles can be cut by as much a 90%.In addition combining the software development tools with logicsimulation, the co-verification environment delivers high performanceco-verification months ahead of a discrete solution. The co-verificationenvironment enables software and hardware development to be parallelactivities, removing the software from the critical path, and reducingthe risk of hardware prototype iterations resulting from integrationerrors.

[0075] The FPGA design software in System Designer is based on Atmel'sIDS 7.0. It includes Macro Generators, HDLPlanner™ push button automaticplace and route, floor planning, timing driven design, both static andinteractive timing analysis, bitstream utilities, incremental designchange capability, architecture mapping, back annotation, an interactivelayout editor and a library manager.

[0076] System Designer comes with push button macro generators thatfacilitate the design of fully parameterizable hard or soft intellectualproperty (IP) cores for the FPSLIC FPGA array. The macro generatorcalculates power consumption, area and pitch of the macros. All Atmelmacros are optimized for the AT40K architecture. More than fifty macrogenerators are available in System Designer that can be used to createfully parameterized IP cores of virtually any complexity. The macrogenerators include: adders, FIFOs, counters, comparators, decoders, flipflops, latches, RAMs, CRC, integer dividers, linear feedback shiftregisters, (LSRs), fast pre-scale counters, accumulators, deductors,multipliers, muxes, negation, shifters, ROMs, subtractors and tri-statebus control. These functions can be parameterized for word-width, poweror area and trade-offs can be made easily.

[0077] System Designer's macro generators are invoked from pull-downmenus so the designer need only point and click to create the desiredfunctionality. Once the macro generator is invoked, a dialog box letsthe designer specify any parameters that are appropriate to the macro.

[0078] Designers can also download from Atmel's WWW site details ofcomplex IP cores, such as FIR filters, IIR filters, convolvers and otherfunctions that are available for free from Atmel's growing library ofFPGA intellectual property.

[0079] Atmel's HDLPlanner tool automates the development of FPGA VHDL orVerilog descriptions by automatically generating syntactically correctVerilog or VHDL code. HDLPlanner can generate HDL descriptions frommacros developed with System Designer's macro generator tools. Anydesign done using HDL Planner is completely device and technologyindependent and can be synthesized, using industry standardsynthesis-tools, for implementation in any ASIC or FPGA. HDL-Plannerautomatically instantiates components that are optimized for AtmelFPGAs. The instantiated components are completely transparent to theuser. Although they are architecturally optimized for the AT40K FPGAlogic, instantiated components have no affect on the technologyindependence of the HDL designs.

[0080] FPSLIC Firmware Design and Debugging

[0081] Atmel's AVR software design environment is an integral part ofthe System Designer EDA Tool Suite. It enables the development,execution and debugging of AVR programs using a built-in instruction setsimulator.

[0082] AVR Studio provides a “Source” window with the program code and apointer that marks the code currently being executed. It has a varietyof views that assist in debugging the design. These include windowsthat: display the values of defined symbols, including instancevariables in a C-program; display the contents of all 32 of the AVR'sregisters; report messages issued by AVR Studio; allow the user the toview and modify the contents of all AVR memory resources; show theaddress of the next instruction to be executed, the value of the stack;pointer, and the number of clock cycles that have elapsed since the lastreset; show the status of peripheral devices; display information aboutany AVR timer/counters; show the three I/O registers on each of the AVRports; show the status of on-chip peripherals (UARTs, SPI).

[0083] FPSLIC Co-verification routines allow the HDL simulator and theAVR instruction set simulation to run simultaneously and interactively.Since the hardware and software are designed and debugged together, thelikelihood of getting a design that works the first time is greatlyincreased. Total system development time can be cut by 10% to 90%. TheFPSLIC System Designer software suite is unique in its completeness andability to accelerate time to market.

[0084] The FPSLICs EDA environment is based on a systems approach todesign methodology, including co-verification of the hardware andsoftware.

[0085]FIG. 2 broadly shows co-verification 30 of a hardware flow andsimulation 31 and software flow and simulation 32. The hardware flow andsimulation is a hardware implementation of the FPSLIC device 20. Thesoftware flow and simulation is a software implementation on the FPSLICdevice 20 or a processor or computer. The software implementation 32,however, typically is a pure software implementation of the FPSLICdevice 20 on the FPSLIC device.

[0086] The co-verification 30 the software flow and simulation 32 withthe hardware flow and simulation 31 is the heart of the presentinvention. Software flow and simulation 32 is readily availablesoftware. The co-verification 30 supports the ability to simulate thehardware part of the FPSLIC design and the software side of the FPSLICdesign in one unified environment. If something in the FPSLIC device 20changes during a design, a modification can be made in the software flowand simulation 32.

[0087] In the exemplary arrangement shown in FIG. 3, a method forco-verifying a hardware simulation of a field-programmable-gate arrayand a software simulation of the field-programmable-gate array, isprovided. The method comprises the steps of simulating, in hardware, aFPSLIC device.

[0088] More particularly, FPSLIC software for running the FPSLIC deviceis inputted 41 to the FPSLIC device. The FPSLIC software is a simulationof the application for which the device will be used. The FPSLIC devicesoftware is run as a simulation 42. If there were a problem with thesimulation 43, then the FPSLIC device software can be modified oraltered, re-inputted 41 and the simulation 412 run again.

[0089] If there were no problem with the FPSLIC device software, then asynthesis 44, and from the synthesis, a netlist 45 is generated of theFPSLIC device software. From the netlist 45, place and route 46 aregenerated, and a resulting simulator port layout 47. On the FPSLICdevice, the contents of the simulator port layout 47 are checked for aproblem 48, and if there were a problem, then alterations can be made inthe place and route 46 or to the FPSLIC device software at the input 41.

[0090] If there were no problems 48 with the simulator port layout 47,then a bit stream can be generated for implementing the FPSLIC device insilicon 60.

[0091] In software, the method separately includes the steps, using aprocessor or computer, of simulating, with an instruction-set simulator,the FPSLIC device, and outputting register contents from theinstruction-set software. More particularly, a high-level code 51 iswritten for simulating the FPSLIC device. The high-level code may be,for example, C language. The high-level code 51 is compiled by acompiler 52 as assembly code. Alternatively, Assembly code may bewritten for the FPSLIC device, and the process starts with the assemblycode 53.

[0092] The instruction set simulator 54 runs the assembly code as asimulation of the FPSLIC device. The instructions set simulator canoutput contents for registers 61, peripherals 62, UART ports, and otherdesired check points in the software. The outputs and instruction setsimulator 54 are checked for problems 55. If there were a problem, thehigh-level code or assembly code can be modified, and theinstruction-set simulator 54 run again.

[0093] If there were no problems 55, then the assembly code is outputtedas object code 56, and then program code 57. The program code 57 is usedto manufacture the FPSLIC device in silicon 60.

[0094] The method further includes verifying contents from thesimulator-port layout with the register contents. The verification isdepicted as examine content 50 of the register counters 61, peripherals62 and UART ports 63, as well as the simulator layout 47. Theco-verification speeds up the process to realizing the FPSLIC insilicon, since the software flow and simulation and the hardware flowand simulation are verified interactively.

[0095] It will be apparent to those skilled in the art that variousmodifications can be made to the software tool for allowing fieldprogrammable system level devices of the instant invention withoutdeparting from the scope or spirit of the invention, and it is intendedthat the present invention cover modifications and variations of thesoftware tool for allowing field programmable system level devicesprovided they come within the scope of the appended claims and theirequivalents.

We claim:
 1. A method for co-verifying a hardware simulation of afield-programmable-system-level integrated circuit (FPSLIC) and asoftware simulation of the field-programmable-system-level integratedcircuit, comprising the steps of: simulating in hardware a FPSLICdevice; generating, from the simulation in hardware, a simulator-portlayout of the FPSLIC device; simulating, with an instruction-setsimulator, in software the FPSLIC device; outputting register contentsfrom the instruction-set software, from the simulation in software; andverifying contents from the simulator-port layout with the registercontents.
 2. The method as set forth in claim 1 , further including thesteps of: outputting peripheral contents from the instruction-setsimulator, from the simulation in software; and verifying contents fromthe simulator-port layout with the peripheral contents.
 3. The method asset forth in claim 1 , further including the steps of: outputting UARTcontents from the instruction-set simulator, from the simulation insoftware; and verifying contents from the simulator-port layout with theUART contents.
 4. A system for co-verifying a hardware simulation of afield-programmable-system-level integrated circuit (FPSLIC) and asoftware simulation of the field-programmable-system-level integratedcircuit, comprising: a hardware simulator for simulating a FPSLICdevice, with the hardware simulator having a simulator-port layout ofthe FPSLIC device; a software simulator for simulating the FPSLICdevice, with software simulator having an instruction-set simulator foroutputting register contents; and verification software for verifyingcontents from the simulator-port layout with the register contents. 5.The system as set forth in claim 4 , with: said instruction-setsimulator outputting peripheral contents; and said verification softwarefor verifying contents from the simulator-port layout with theperipheral contents.
 6. The system as set forth in claim 4 , with: saidinstruction-set simulator outputting UART contents; and saidverification software for verifying contents from the simulator-portlayout with the UART contents.